{"id":399530,"date":"2024-10-20T04:43:28","date_gmt":"2024-10-20T04:43:28","guid":{"rendered":"https:\/\/pdfstandards.shop\/product\/uncategorized\/ieee-1364-2005\/"},"modified":"2024-10-26T08:31:47","modified_gmt":"2024-10-26T08:31:47","slug":"ieee-1364-2005","status":"publish","type":"product","link":"https:\/\/pdfstandards.shop\/product\/publishers\/ieee\/ieee-1364-2005\/","title":{"rendered":"IEEE 1364-2005"},"content":{"rendered":"

Revision Standard – Superseded. The Verilog hardware description language (HDL) is defined in this standard. Verilog HDL is a formal notation intended for use in all phases of the creation of electronic systems. Because it is both machine-readable and human-readable, it supports the development, verification, synthesis, and testing of hardware designs; the communication of hardware design data; and the maintenance, modification, and procurement of hardware. The primary audiences for this standard are the implementers of tools supporting the language and advanced users of the language.<\/p>\n

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PDF Pages<\/th>\nPDF Title<\/th>\n<\/tr>\n
3<\/td>\nIEEE Standard for Verilog\u00ae Hardware Description Language <\/td>\n<\/tr>\n
5<\/td>\nIntroduction <\/td>\n<\/tr>\n
6<\/td>\nNotice to users
Errata
Interpretations
Patents
Participants <\/td>\n<\/tr>\n
9<\/td>\nContents <\/td>\n<\/tr>\n
23<\/td>\nList of Figures <\/td>\n<\/tr>\n
25<\/td>\nList of Tables <\/td>\n<\/tr>\n
28<\/td>\nList of Syntax Boxes <\/td>\n<\/tr>\n
31<\/td>\nIEEE Standard for Verilog\u00ae Hardware Description Language
1. Overview
1.1 Scope
1.2 Conventions used in this standard <\/td>\n<\/tr>\n
32<\/td>\n1.3 Syntactic description <\/td>\n<\/tr>\n
33<\/td>\n1.4 Use of color in this standard
1.5 Contents of this standard <\/td>\n<\/tr>\n
35<\/td>\n1.6 Deprecated clauses
1.7 Header file listings
1.8 Examples
1.9 Prerequisites <\/td>\n<\/tr>\n
36<\/td>\n2. Normative references <\/td>\n<\/tr>\n
38<\/td>\n3. Lexical conventions
3.1 Lexical tokens
3.2 White space
3.3 Comments
3.4 Operators <\/td>\n<\/tr>\n
39<\/td>\n3.5 Numbers <\/td>\n<\/tr>\n
40<\/td>\n3.5.1 Integer constants <\/td>\n<\/tr>\n
42<\/td>\n3.5.2 Real constants
3.5.3 Conversion
3.6 Strings <\/td>\n<\/tr>\n
43<\/td>\n3.6.1 String variable declaration
3.6.2 String manipulation
3.6.3 Special characters in strings <\/td>\n<\/tr>\n
44<\/td>\n3.7 Identifiers, keywords, and system names
3.7.1 Escaped identifiers <\/td>\n<\/tr>\n
45<\/td>\n3.7.2 Keywords
3.7.3 System tasks and functions
3.7.4 Compiler directives <\/td>\n<\/tr>\n
46<\/td>\n3.8 Attributes
3.8.1 Examples <\/td>\n<\/tr>\n
48<\/td>\n3.8.2 Syntax <\/td>\n<\/tr>\n
51<\/td>\n4. Data types
4.1 Value set
4.2 Nets and variables
4.2.1 Net declarations <\/td>\n<\/tr>\n
53<\/td>\n4.2.2 Variable declarations <\/td>\n<\/tr>\n
54<\/td>\n4.3 Vectors
4.3.1 Specifying vectors
4.3.2 Vector net accessibility <\/td>\n<\/tr>\n
55<\/td>\n4.4 Strengths
4.4.1 Charge strength
4.4.2 Drive strength
4.5 Implicit declarations <\/td>\n<\/tr>\n
56<\/td>\n4.6 Net types
4.6.1 Wire and tri nets <\/td>\n<\/tr>\n
57<\/td>\n4.6.2 Wired nets <\/td>\n<\/tr>\n
58<\/td>\n4.6.3 Trireg net <\/td>\n<\/tr>\n
61<\/td>\n4.6.4 Tri0 and tri1 nets
4.6.5 Unresolved nets <\/td>\n<\/tr>\n
62<\/td>\n4.6.6 Supply nets
4.7 Regs
4.8 Integers, reals, times, and realtimes <\/td>\n<\/tr>\n
63<\/td>\n4.8.1 Operators and real numbers
4.8.2 Conversion <\/td>\n<\/tr>\n
64<\/td>\n4.9 Arrays
4.9.1 Net arrays
4.9.2 reg and variable arrays <\/td>\n<\/tr>\n
65<\/td>\n4.9.3 Memories
4.10 Parameters <\/td>\n<\/tr>\n
66<\/td>\n4.10.1 Module parameters <\/td>\n<\/tr>\n
67<\/td>\n4.10.2 Local parameters (localparam) <\/td>\n<\/tr>\n
68<\/td>\n4.10.3 Specify parameters <\/td>\n<\/tr>\n
69<\/td>\n4.11 Name spaces <\/td>\n<\/tr>\n
71<\/td>\n5. Expressions
5.1 Operators <\/td>\n<\/tr>\n
72<\/td>\n5.1.1 Operators with real operands <\/td>\n<\/tr>\n
73<\/td>\n5.1.2 Operator precedence <\/td>\n<\/tr>\n
74<\/td>\n5.1.3 Using integer numbers in expressions <\/td>\n<\/tr>\n
75<\/td>\n5.1.4 Expression evaluation order
5.1.5 Arithmetic operators <\/td>\n<\/tr>\n
77<\/td>\n5.1.6 Arithmetic expressions with regs and integers <\/td>\n<\/tr>\n
78<\/td>\n5.1.7 Relational operators <\/td>\n<\/tr>\n
79<\/td>\n5.1.8 Equality operators
5.1.9 Logical operators <\/td>\n<\/tr>\n
80<\/td>\n5.1.10 Bitwise operators <\/td>\n<\/tr>\n
81<\/td>\n5.1.11 Reduction operators <\/td>\n<\/tr>\n
83<\/td>\n5.1.12 Shift operators
5.1.13 Conditional operator <\/td>\n<\/tr>\n
84<\/td>\n5.1.14 Concatenations <\/td>\n<\/tr>\n
85<\/td>\n5.2 Operands <\/td>\n<\/tr>\n
86<\/td>\n5.2.1 Vector bit-select and part-select addressing <\/td>\n<\/tr>\n
87<\/td>\n5.2.2 Array and memory addressing <\/td>\n<\/tr>\n
88<\/td>\n5.2.3 Strings <\/td>\n<\/tr>\n
91<\/td>\n5.3 Minimum, typical, and maximum delay expressions <\/td>\n<\/tr>\n
92<\/td>\n5.4 Expression bit lengths
5.4.1 Rules for expression bit lengths <\/td>\n<\/tr>\n
93<\/td>\n5.4.2 Example of expression bit-length problem <\/td>\n<\/tr>\n
94<\/td>\n5.4.3 Example of self-determined expressions
5.5 Signed expressions <\/td>\n<\/tr>\n
95<\/td>\n5.5.1 Rules for expression types
5.5.2 Steps for evaluating an expression <\/td>\n<\/tr>\n
96<\/td>\n5.5.3 Steps for evaluating an assignment
5.5.4 Handling X and Z in signed expressions
5.6 Assignments and truncation <\/td>\n<\/tr>\n
98<\/td>\n6. Assignments
6.1 Continuous assignments <\/td>\n<\/tr>\n
99<\/td>\n6.1.1 The net declaration assignment
6.1.2 The continuous assignment statement <\/td>\n<\/tr>\n
101<\/td>\n6.1.3 Delays
6.1.4 Strength <\/td>\n<\/tr>\n
102<\/td>\n6.2 Procedural assignments
6.2.1 Variable declaration assignment <\/td>\n<\/tr>\n
103<\/td>\n6.2.2 Variable declaration syntax <\/td>\n<\/tr>\n
104<\/td>\n7. Gate- and switch-level modeling
7.1 Gate and switch declaration syntax <\/td>\n<\/tr>\n
106<\/td>\n7.1.1 The gate type specification
7.1.2 The drive strength specification <\/td>\n<\/tr>\n
107<\/td>\n7.1.3 The delay specification
7.1.4 The primitive instance identifier
7.1.5 The range specification <\/td>\n<\/tr>\n
108<\/td>\n7.1.6 Primitive instance connection list <\/td>\n<\/tr>\n
110<\/td>\n7.2 and, nand, nor, or, xor, and xnor gates <\/td>\n<\/tr>\n
111<\/td>\n7.3 buf and not gates <\/td>\n<\/tr>\n
112<\/td>\n7.4 bufif1, bufif0, notif1, and notif0 gates <\/td>\n<\/tr>\n
113<\/td>\n7.5 MOS switches <\/td>\n<\/tr>\n
114<\/td>\n7.6 Bidirectional pass switches <\/td>\n<\/tr>\n
115<\/td>\n7.7 CMOS switches <\/td>\n<\/tr>\n
116<\/td>\n7.8 pullup and pulldown sources
7.9 Logic strength modeling <\/td>\n<\/tr>\n
118<\/td>\n7.10 Strengths and values of combined signals
7.10.1 Combined signals of unambiguous strength <\/td>\n<\/tr>\n
119<\/td>\n7.10.2 Ambiguous strengths: sources and combinations <\/td>\n<\/tr>\n
124<\/td>\n7.10.3 Ambiguous strength signals and unambiguous signals <\/td>\n<\/tr>\n
128<\/td>\n7.10.4 Wired logic net types <\/td>\n<\/tr>\n
130<\/td>\n7.11 Strength reduction by nonresistive devices
7.12 Strength reduction by resistive devices
7.13 Strengths of net types
7.13.1 tri0 and tri1 net strengths
7.13.2 trireg strength <\/td>\n<\/tr>\n
131<\/td>\n7.13.3 supply0 and supply1 net strengths
7.14 Gate and net delays <\/td>\n<\/tr>\n
132<\/td>\n7.14.1 min:typ:max delays <\/td>\n<\/tr>\n
133<\/td>\n7.14.2 trireg net charge decay <\/td>\n<\/tr>\n
135<\/td>\n8. User-defined primitives (UDPs)
8.1 UDP definition <\/td>\n<\/tr>\n
137<\/td>\n8.1.1 UDP header
8.1.2 UDP port declarations
8.1.3 Sequential UDP initial statement
8.1.4 UDP state table <\/td>\n<\/tr>\n
138<\/td>\n8.1.5 Z values in UDP
8.1.6 Summary of symbols <\/td>\n<\/tr>\n
139<\/td>\n8.2 Combinational UDPs <\/td>\n<\/tr>\n
140<\/td>\n8.3 Level-sensitive sequential UDPs
8.4 Edge-sensitive sequential UDPs <\/td>\n<\/tr>\n
141<\/td>\n8.5 Sequential UDP initialization <\/td>\n<\/tr>\n
143<\/td>\n8.6 UDP instances <\/td>\n<\/tr>\n
144<\/td>\n8.7 Mixing level-sensitive and edge-sensitive descriptions <\/td>\n<\/tr>\n
145<\/td>\n8.8 Level-sensitive dominance <\/td>\n<\/tr>\n
146<\/td>\n9. Behavioral modeling
9.1 Behavioral model overview <\/td>\n<\/tr>\n
147<\/td>\n9.2 Procedural assignments
9.2.1 Blocking procedural assignments <\/td>\n<\/tr>\n
148<\/td>\n9.2.2 The nonblocking procedural assignment <\/td>\n<\/tr>\n
152<\/td>\n9.3 Procedural continuous assignments <\/td>\n<\/tr>\n
153<\/td>\n9.3.1 The assign and deassign procedural statements <\/td>\n<\/tr>\n
154<\/td>\n9.3.2 The force and release procedural statements <\/td>\n<\/tr>\n
155<\/td>\n9.4 Conditional statement <\/td>\n<\/tr>\n
156<\/td>\n9.4.1 If-else-if construct <\/td>\n<\/tr>\n
157<\/td>\n9.5 Case statement <\/td>\n<\/tr>\n
158<\/td>\n9.5.1 Case statement with do-not-cares <\/td>\n<\/tr>\n
159<\/td>\n9.5.2 Constant expression in case statement <\/td>\n<\/tr>\n
160<\/td>\n9.6 Looping statements <\/td>\n<\/tr>\n
161<\/td>\n9.7 Procedural timing controls <\/td>\n<\/tr>\n
162<\/td>\n9.7.1 Delay control
9.7.2 Event control <\/td>\n<\/tr>\n
163<\/td>\n9.7.3 Named events <\/td>\n<\/tr>\n
164<\/td>\n9.7.4 Event or operator
9.7.5 Implicit event_expression list <\/td>\n<\/tr>\n
166<\/td>\n9.7.6 Level-sensitive event control
9.7.7 Intra-assignment timing controls <\/td>\n<\/tr>\n
169<\/td>\n9.8 Block statements <\/td>\n<\/tr>\n
170<\/td>\n9.8.1 Sequential blocks <\/td>\n<\/tr>\n
171<\/td>\n9.8.2 Parallel blocks
9.8.3 Block names <\/td>\n<\/tr>\n
172<\/td>\n9.8.4 Start and finish times <\/td>\n<\/tr>\n
173<\/td>\n9.9 Structured procedures
9.9.1 Initial construct <\/td>\n<\/tr>\n
174<\/td>\n9.9.2 Always construct <\/td>\n<\/tr>\n
175<\/td>\n10. Tasks and functions
10.1 Distinctions between tasks and functions
10.2 Tasks and task enabling <\/td>\n<\/tr>\n
176<\/td>\n10.2.1 Task declarations <\/td>\n<\/tr>\n
177<\/td>\n10.2.2 Task enabling and argument passing <\/td>\n<\/tr>\n
179<\/td>\n10.2.3 Task memory usage and concurrent activation <\/td>\n<\/tr>\n
180<\/td>\n10.3 Disabling of named blocks and tasks <\/td>\n<\/tr>\n
182<\/td>\n10.4 Functions and function calling
10.4.1 Function declarations <\/td>\n<\/tr>\n
184<\/td>\n10.4.2 Returning a value from a function <\/td>\n<\/tr>\n
185<\/td>\n10.4.3 Calling a function
10.4.4 Function rules <\/td>\n<\/tr>\n
186<\/td>\n10.4.5 Use of constant functions <\/td>\n<\/tr>\n
188<\/td>\n11. Scheduling semantics
11.1 Execution of a model
11.2 Event simulation
11.3 The stratified event queue <\/td>\n<\/tr>\n
189<\/td>\n11.4 Verilog simulation reference model <\/td>\n<\/tr>\n
190<\/td>\n11.4.1 Determinism
11.4.2 Nondeterminism
11.5 Race conditions <\/td>\n<\/tr>\n
191<\/td>\n11.6 Scheduling implication of assignments
11.6.1 Continuous assignment
11.6.2 Procedural continuous assignment
11.6.3 Blocking assignment
11.6.4 Nonblocking assignment
11.6.5 Switch (transistor) processing <\/td>\n<\/tr>\n
192<\/td>\n11.6.6 Port connections
11.6.7 Functions and tasks <\/td>\n<\/tr>\n
193<\/td>\n12. Hierarchical structures
12.1 Modules <\/td>\n<\/tr>\n
195<\/td>\n12.1.1 Top-level modules
12.1.2 Module instantiation <\/td>\n<\/tr>\n
197<\/td>\n12.2 Overriding module parameter values <\/td>\n<\/tr>\n
198<\/td>\n12.2.1 defparam statement <\/td>\n<\/tr>\n
200<\/td>\n12.2.2 Module instance parameter value assignment <\/td>\n<\/tr>\n
203<\/td>\n12.2.3 Parameter dependence
12.3 Ports
12.3.1 Port definition <\/td>\n<\/tr>\n
204<\/td>\n12.3.2 List of ports
12.3.3 Port declarations <\/td>\n<\/tr>\n
206<\/td>\n12.3.4 List of ports declarations
12.3.5 Connecting module instance ports by ordered list <\/td>\n<\/tr>\n
207<\/td>\n12.3.6 Connecting module instance ports by name <\/td>\n<\/tr>\n
208<\/td>\n12.3.7 Real numbers in port connections
12.3.8 Connecting dissimilar ports <\/td>\n<\/tr>\n
209<\/td>\n12.3.9 Port connection rules
12.3.10 Net types resulting from dissimilar port connections <\/td>\n<\/tr>\n
211<\/td>\n12.3.11 Connecting signed values via ports
12.4 Generate constructs <\/td>\n<\/tr>\n
213<\/td>\n12.4.1 Loop generate constructs <\/td>\n<\/tr>\n
216<\/td>\n12.4.2 Conditional generate constructs <\/td>\n<\/tr>\n
220<\/td>\n12.4.3 External names for unnamed generate blocks <\/td>\n<\/tr>\n
221<\/td>\n12.5 Hierarchical names <\/td>\n<\/tr>\n
223<\/td>\n12.6 Upwards name referencing <\/td>\n<\/tr>\n
225<\/td>\n12.7 Scope rules <\/td>\n<\/tr>\n
227<\/td>\n12.8 Elaboration
12.8.1 Order of elaboration
12.8.2 Early resolution of hierarchical names <\/td>\n<\/tr>\n
229<\/td>\n13. Configuring the contents of a design
13.1 Introduction
13.1.1 Library notation <\/td>\n<\/tr>\n
230<\/td>\n13.1.2 Basic configuration elements
13.2 Libraries
13.2.1 Specifying libraries-the library map file <\/td>\n<\/tr>\n
232<\/td>\n13.2.2 Using multiple library map files
13.2.3 Mapping source files to libraries
13.3 Configurations
13.3.1 Basic configuration syntax <\/td>\n<\/tr>\n
235<\/td>\n13.3.2 Hierarchical configurations
13.4 Using libraries and configs
13.4.1 Precompiling in a single-pass use model <\/td>\n<\/tr>\n
236<\/td>\n13.4.2 Elaboration-time compiling in a single-pass use model
13.4.3 Precompiling using a separate compilation tool
13.4.4 Command line considerations
13.5 Configuration examples <\/td>\n<\/tr>\n
237<\/td>\n13.5.1 Default configuration from library map file
13.5.2 Using default clause
13.5.3 Using cell clause <\/td>\n<\/tr>\n
238<\/td>\n13.5.4 Using instance clause
13.5.5 Using hierarchical config
13.6 Displaying library binding information <\/td>\n<\/tr>\n
239<\/td>\n13.7 Library mapping examples
13.7.1 Using the command line to control library searching
13.7.2 File path specification examples
13.7.3 Resolving multiple path specifications <\/td>\n<\/tr>\n
241<\/td>\n14. Specify blocks
14.1 Specify block declaration <\/td>\n<\/tr>\n
242<\/td>\n14.2 Module path declarations <\/td>\n<\/tr>\n
243<\/td>\n14.2.1 Module path restrictions
14.2.2 Simple module paths <\/td>\n<\/tr>\n
244<\/td>\n14.2.3 Edge-sensitive paths <\/td>\n<\/tr>\n
245<\/td>\n14.2.4 State-dependent paths <\/td>\n<\/tr>\n
249<\/td>\n14.2.5 Full connection and parallel connection paths <\/td>\n<\/tr>\n
250<\/td>\n14.2.6 Declaring multiple module paths in a single statement
14.2.7 Module path polarity <\/td>\n<\/tr>\n
252<\/td>\n14.3 Assigning delays to module paths
14.3.1 Specifying transition delays on module paths <\/td>\n<\/tr>\n
254<\/td>\n14.3.2 Specifying x transition delays <\/td>\n<\/tr>\n
255<\/td>\n14.3.3 Delay selection
14.4 Mixing module path delays and distributed delays <\/td>\n<\/tr>\n
256<\/td>\n14.5 Driving wired logic <\/td>\n<\/tr>\n
258<\/td>\n14.6 Detailed control of pulse filtering behavior <\/td>\n<\/tr>\n
259<\/td>\n14.6.1 Specify block control of pulse limit values <\/td>\n<\/tr>\n
260<\/td>\n14.6.2 Global control of pulse limit values
14.6.3 SDF annotation of pulse limit values
14.6.4 Detailed pulse control capabilities <\/td>\n<\/tr>\n
267<\/td>\n15. Timing checks
15.1 Overview <\/td>\n<\/tr>\n
270<\/td>\n15.2 Timing checks using a stability window <\/td>\n<\/tr>\n
271<\/td>\n15.2.1 $setup <\/td>\n<\/tr>\n
272<\/td>\n15.2.2 $hold <\/td>\n<\/tr>\n
273<\/td>\n15.2.3 $setuphold <\/td>\n<\/tr>\n
275<\/td>\n15.2.4 $removal <\/td>\n<\/tr>\n
276<\/td>\n15.2.5 $recovery <\/td>\n<\/tr>\n
277<\/td>\n15.2.6 $recrem <\/td>\n<\/tr>\n
278<\/td>\n15.3 Timing checks for clock and control signals <\/td>\n<\/tr>\n
279<\/td>\n15.3.1 $skew <\/td>\n<\/tr>\n
280<\/td>\n15.3.2 $timeskew <\/td>\n<\/tr>\n
282<\/td>\n15.3.3 $fullskew <\/td>\n<\/tr>\n
285<\/td>\n15.3.4 $width <\/td>\n<\/tr>\n
286<\/td>\n15.3.5 $period <\/td>\n<\/tr>\n
287<\/td>\n15.3.6 $nochange <\/td>\n<\/tr>\n
288<\/td>\n15.4 Edge-control specifiers <\/td>\n<\/tr>\n
289<\/td>\n15.5 Notifiers: user-defined responses to timing violations <\/td>\n<\/tr>\n
291<\/td>\n15.5.1 Requirements for accurate simulation <\/td>\n<\/tr>\n
293<\/td>\n15.5.2 Conditions in negative timing checks <\/td>\n<\/tr>\n
294<\/td>\n15.5.3 Notifiers in negative timing checks
15.5.4 Option behavior <\/td>\n<\/tr>\n
295<\/td>\n15.6 Enabling timing checks with conditioned events <\/td>\n<\/tr>\n
296<\/td>\n15.7 Vector signals in timing checks
15.8 Negative timing checks <\/td>\n<\/tr>\n
299<\/td>\n16. Backannotation using the standard delay format (SDF)
16.1 The SDF annotator
16.2 Mapping of SDF constructs to Verilog
16.2.1 Mapping of SDF delay constructs to Verilog declarations <\/td>\n<\/tr>\n
301<\/td>\n16.2.2 Mapping of SDF timing check constructs to Verilog <\/td>\n<\/tr>\n
302<\/td>\n16.2.3 SDF annotation of specparams <\/td>\n<\/tr>\n
303<\/td>\n16.2.4 SDF annotation of interconnect delays <\/td>\n<\/tr>\n
304<\/td>\n16.3 Multiple annotations <\/td>\n<\/tr>\n
305<\/td>\n16.4 Multiple SDF files
16.5 Pulse limit annotation <\/td>\n<\/tr>\n
306<\/td>\n16.6 SDF to Verilog delay value mapping <\/td>\n<\/tr>\n
307<\/td>\n17. System tasks and functions <\/td>\n<\/tr>\n
308<\/td>\n17.1 Display system tasks
17.1.1 The display and write tasks <\/td>\n<\/tr>\n
315<\/td>\n17.1.2 Strobed monitoring <\/td>\n<\/tr>\n
316<\/td>\n17.1.3 Continuous monitoring
17.2 File input-output system tasks and functions <\/td>\n<\/tr>\n
317<\/td>\n17.2.1 Opening and closing files <\/td>\n<\/tr>\n
318<\/td>\n17.2.2 File output system tasks <\/td>\n<\/tr>\n
319<\/td>\n17.2.3 Formatting data to a string <\/td>\n<\/tr>\n
320<\/td>\n17.2.4 Reading data from a file <\/td>\n<\/tr>\n
324<\/td>\n17.2.5 File positioning <\/td>\n<\/tr>\n
325<\/td>\n17.2.6 Flushing output
17.2.7 I\/O error status
17.2.8 Detecting EOF <\/td>\n<\/tr>\n
326<\/td>\n17.2.9 Loading memory data from a file <\/td>\n<\/tr>\n
327<\/td>\n17.2.10 Loading timing data from an SDF file <\/td>\n<\/tr>\n
328<\/td>\n17.3 Timescale system tasks <\/td>\n<\/tr>\n
329<\/td>\n17.3.1 $printtimescale <\/td>\n<\/tr>\n
330<\/td>\n17.3.2 $timeformat <\/td>\n<\/tr>\n
332<\/td>\n17.4 Simulation control system tasks
17.4.1 $finish
17.4.2 $stop <\/td>\n<\/tr>\n
333<\/td>\n17.5 Programmable logic array (PLA) modeling system tasks
17.5.1 Array types <\/td>\n<\/tr>\n
334<\/td>\n17.5.2 Array logic types
17.5.3 Logic array personality declaration and loading
17.5.4 Logic array personality formats <\/td>\n<\/tr>\n
337<\/td>\n17.6 Stochastic analysis tasks
17.6.1 $q_initialize
17.6.2 $q_add
17.6.3 $q_remove <\/td>\n<\/tr>\n
338<\/td>\n17.6.4 $q_full
17.6.5 $q_exam
17.6.6 Status codes <\/td>\n<\/tr>\n
339<\/td>\n17.7 Simulation time system functions
17.7.1 $time
17.7.2 $stime <\/td>\n<\/tr>\n
340<\/td>\n17.7.3 $realtime
17.8 Conversion functions <\/td>\n<\/tr>\n
341<\/td>\n17.9 Probabilistic distribution functions
17.9.1 $random function <\/td>\n<\/tr>\n
342<\/td>\n17.9.2 $dist_ functions <\/td>\n<\/tr>\n
343<\/td>\n17.9.3 Algorithm for probabilistic distribution functions <\/td>\n<\/tr>\n
350<\/td>\n17.10 Command line input
17.10.1 $test$plusargs (string) <\/td>\n<\/tr>\n
351<\/td>\n17.10.2 $value$plusargs (user_string, variable) <\/td>\n<\/tr>\n
353<\/td>\n17.11 Math functions
17.11.1 Integer math functions
17.11.2 Real math functions <\/td>\n<\/tr>\n
355<\/td>\n18. Value change dump (VCD) files
18.1 Creating four-state VCD file
18.1.1 Specifying name of dump file ($dumpfile) <\/td>\n<\/tr>\n
356<\/td>\n18.1.2 Specifying variables to be dumped ($dumpvars) <\/td>\n<\/tr>\n
357<\/td>\n18.1.3 Stopping and resuming the dump ($dumpoff\/$dumpon) <\/td>\n<\/tr>\n
358<\/td>\n18.1.4 Generating a checkpoint ($dumpall)
18.1.5 Limiting size of dump file ($dumplimit)
18.1.6 Reading dump file during simulation ($dumpflush) <\/td>\n<\/tr>\n
359<\/td>\n18.2 Format of four-state VCD file <\/td>\n<\/tr>\n
360<\/td>\n18.2.1 Syntax of four-state VCD file <\/td>\n<\/tr>\n
361<\/td>\n18.2.2 Formats of variable values <\/td>\n<\/tr>\n
362<\/td>\n18.2.3 Description of keyword commands <\/td>\n<\/tr>\n
367<\/td>\n18.2.4 Four-state VCD file format example <\/td>\n<\/tr>\n
368<\/td>\n18.3 Creating extended VCD file
18.3.1 Specifying dump file name and ports to be dumped ($dumpports) <\/td>\n<\/tr>\n
369<\/td>\n18.3.2 Stopping and resuming the dump ($dumpportsoff\/$dumpportson) <\/td>\n<\/tr>\n
370<\/td>\n18.3.3 Generating a checkpoint ($dumpportsall)
18.3.4 Limiting size of dump file ($dumpportslimit) <\/td>\n<\/tr>\n
371<\/td>\n18.3.5 Reading dump file during simulation ($dumpportsflush)
18.3.6 Description of keyword commands
18.3.7 General rules for extended VCD system tasks <\/td>\n<\/tr>\n
372<\/td>\n18.4 Format of extended VCD file
18.4.1 Syntax of extended VCD file <\/td>\n<\/tr>\n
374<\/td>\n18.4.2 Extended VCD node information <\/td>\n<\/tr>\n
376<\/td>\n18.4.3 Value changes <\/td>\n<\/tr>\n
377<\/td>\n18.4.4 Extended VCD file format example <\/td>\n<\/tr>\n
379<\/td>\n19. Compiler directives
19.1 `celldefine and `endcelldefine
19.2 `default_nettype <\/td>\n<\/tr>\n
380<\/td>\n19.3 `define and `undef
19.3.1 `define <\/td>\n<\/tr>\n
382<\/td>\n19.3.2 `undef
19.4 `ifdef, `else, `elsif, `endif, `ifndef <\/td>\n<\/tr>\n
386<\/td>\n19.5 `include
19.6 `resetall <\/td>\n<\/tr>\n
387<\/td>\n19.7 `line <\/td>\n<\/tr>\n
388<\/td>\n19.8 `timescale <\/td>\n<\/tr>\n
390<\/td>\n19.9 `unconnected_drive and `nounconnected_drive
19.10 `pragma <\/td>\n<\/tr>\n
391<\/td>\n19.10.1 Standard pragmas
19.11 `begin_keywords, `end_keywords <\/td>\n<\/tr>\n
396<\/td>\n20. Programming language interface (PLI) overview
20.1 PLI purpose and history <\/td>\n<\/tr>\n
397<\/td>\n20.2 User-defined system task\/function names
20.3 User-defined system task\/function types
20.4 Overriding built-in system task\/function names
20.5 User-supplied PLI applications <\/td>\n<\/tr>\n
398<\/td>\n20.6 PLI mechanism
20.7 User-defined system task\/function arguments
20.8 PLI include files <\/td>\n<\/tr>\n
399<\/td>\n21. PLI TF and ACC interface mechanism (deprecated) <\/td>\n<\/tr>\n
400<\/td>\n22. Using ACC routines (deprecated) <\/td>\n<\/tr>\n
401<\/td>\n23. ACC routine definitions (deprecated) <\/td>\n<\/tr>\n
402<\/td>\n24. Using TF routines (deprecated) <\/td>\n<\/tr>\n
403<\/td>\n25. TF routine definitions (deprecated) <\/td>\n<\/tr>\n
404<\/td>\n26. Using Verilog procedural interface (VPI) routines
26.1 VPI system tasks and functions
26.1.1 sizetf VPI application routine
26.1.2 compiletf VPI application routine <\/td>\n<\/tr>\n
405<\/td>\n26.1.3 calltf VPI application routine
26.1.4 Arguments to sizetf, compiletf, and calltf application routines
26.2 VPI mechanism
26.2.1 VPI callbacks <\/td>\n<\/tr>\n
406<\/td>\n26.2.2 VPI access to Verilog HDL objects and simulation objects
26.2.3 Error handling
26.2.4 Function availability <\/td>\n<\/tr>\n
407<\/td>\n26.2.5 Traversing expressions
26.3 VPI object classifications <\/td>\n<\/tr>\n
408<\/td>\n26.3.1 Accessing object relationships and properties <\/td>\n<\/tr>\n
409<\/td>\n26.3.2 Object type properties <\/td>\n<\/tr>\n
410<\/td>\n26.3.3 Object file and line properties
26.3.4 Delays and values <\/td>\n<\/tr>\n
411<\/td>\n26.3.5 Object protection properties
26.4 List of VPI routines by functional category <\/td>\n<\/tr>\n
413<\/td>\n26.5 Key to data model diagrams <\/td>\n<\/tr>\n
414<\/td>\n26.5.1 Diagram key for objects and classes
26.5.2 Diagram key for accessing properties <\/td>\n<\/tr>\n
415<\/td>\n26.5.3 Diagram key for traversing relationships <\/td>\n<\/tr>\n
416<\/td>\n26.6 Object data model diagrams <\/td>\n<\/tr>\n
417<\/td>\n26.6.1 Module <\/td>\n<\/tr>\n
418<\/td>\n26.6.2 Instance arrays <\/td>\n<\/tr>\n
419<\/td>\n26.6.3 Scope
26.6.4 IO declaration <\/td>\n<\/tr>\n
420<\/td>\n26.6.5 Ports <\/td>\n<\/tr>\n
421<\/td>\n26.6.6 Nets and net arrays <\/td>\n<\/tr>\n
423<\/td>\n26.6.7 Regs and reg arrays <\/td>\n<\/tr>\n
425<\/td>\n26.6.8 Variables <\/td>\n<\/tr>\n
426<\/td>\n26.6.9 Memory
26.6.10 Object range <\/td>\n<\/tr>\n
427<\/td>\n26.6.11 Named event <\/td>\n<\/tr>\n
428<\/td>\n26.6.12 Parameter, specparam <\/td>\n<\/tr>\n
429<\/td>\n26.6.13 Primitive, prim term <\/td>\n<\/tr>\n
430<\/td>\n26.6.14 UDP <\/td>\n<\/tr>\n
431<\/td>\n26.6.15 Module path, path term
26.6.16 Intermodule path <\/td>\n<\/tr>\n
432<\/td>\n26.6.17 Timing check
26.6.18 Task, function declaration <\/td>\n<\/tr>\n
433<\/td>\n26.6.19 Task\/function call <\/td>\n<\/tr>\n
434<\/td>\n26.6.20 Frames <\/td>\n<\/tr>\n
435<\/td>\n26.6.21 Delay terminals
26.6.22 Net drivers and loads <\/td>\n<\/tr>\n
436<\/td>\n26.6.23 Reg drivers and loads
26.6.24 Continuous assignment <\/td>\n<\/tr>\n
437<\/td>\n26.6.25 Simple expressions <\/td>\n<\/tr>\n
438<\/td>\n26.6.26 Expressions <\/td>\n<\/tr>\n
439<\/td>\n26.6.27 Process, block, statement, event statement <\/td>\n<\/tr>\n
440<\/td>\n26.6.28 Assignment
26.6.29 Delay control
26.6.30 Event control <\/td>\n<\/tr>\n
441<\/td>\n26.6.31 Repeat control
26.6.32 While, repeat, wait
26.6.33 For
26.6.34 Forever <\/td>\n<\/tr>\n
442<\/td>\n26.6.35 If, if-else
26.6.36 Case <\/td>\n<\/tr>\n
443<\/td>\n26.6.37 Assign statement, deassign, force, release
26.6.38 Disable <\/td>\n<\/tr>\n
444<\/td>\n26.6.39 Callback
26.6.40 Time queue
26.6.41 Active time format <\/td>\n<\/tr>\n
445<\/td>\n26.6.42 Attributes <\/td>\n<\/tr>\n
446<\/td>\n26.6.43 Iterator <\/td>\n<\/tr>\n
447<\/td>\n26.6.44 Generates <\/td>\n<\/tr>\n
448<\/td>\n27. VPI routine definitions
27.1 vpi_chk_error() <\/td>\n<\/tr>\n
450<\/td>\n27.2 vpi_compare_objects()
27.3 vpi_control() <\/td>\n<\/tr>\n
451<\/td>\n27.4 vpi_flush()
27.5 vpi_free_object() <\/td>\n<\/tr>\n
452<\/td>\n27.6 vpi_get()
27.7 vpi_get_cb_info() <\/td>\n<\/tr>\n
453<\/td>\n27.8 vpi_get_data() <\/td>\n<\/tr>\n
454<\/td>\n27.9 vpi_get_delays() <\/td>\n<\/tr>\n
456<\/td>\n27.10 vpi_get_str() <\/td>\n<\/tr>\n
457<\/td>\n27.11 vpi_get_systf_info() <\/td>\n<\/tr>\n
458<\/td>\n27.12 vpi_get_time() <\/td>\n<\/tr>\n
459<\/td>\n27.13 vpi_get_userdata()
27.14 vpi_get_value() <\/td>\n<\/tr>\n
465<\/td>\n27.15 vpi_get_vlog_info() <\/td>\n<\/tr>\n
466<\/td>\n27.16 vpi_handle() <\/td>\n<\/tr>\n
467<\/td>\n27.17 vpi_handle_by_index() <\/td>\n<\/tr>\n
468<\/td>\n27.18 vpi_handle_by_multi_index()
27.19 vpi_handle_by_name() <\/td>\n<\/tr>\n
469<\/td>\n27.20 vpi_handle_multi()
27.21 vpi_iterate() <\/td>\n<\/tr>\n
470<\/td>\n27.22 vpi_mcd_close() <\/td>\n<\/tr>\n
471<\/td>\n27.23 vpi_mcd_flush()
27.24 vpi_mcd_name() <\/td>\n<\/tr>\n
472<\/td>\n27.25 vpi_mcd_open() <\/td>\n<\/tr>\n
473<\/td>\n27.26 vpi_mcd_printf() <\/td>\n<\/tr>\n
474<\/td>\n27.27 vpi_mcd_vprintf()
27.28 vpi_printf() <\/td>\n<\/tr>\n
475<\/td>\n27.29 vpi_put_data() <\/td>\n<\/tr>\n
477<\/td>\n27.30 vpi_put_delays() <\/td>\n<\/tr>\n
480<\/td>\n27.31 vpi_put_userdata()
27.32 vpi_put_value() <\/td>\n<\/tr>\n
483<\/td>\n27.33 vpi_register_cb() <\/td>\n<\/tr>\n
484<\/td>\n27.33.1 Simulation event callbacks <\/td>\n<\/tr>\n
488<\/td>\n27.33.2 Simulation time callbacks <\/td>\n<\/tr>\n
490<\/td>\n27.33.3 Simulator action or feature callbacks <\/td>\n<\/tr>\n
491<\/td>\n27.34 vpi_register_systf() <\/td>\n<\/tr>\n
492<\/td>\n27.34.1 System task\/function callbacks <\/td>\n<\/tr>\n
493<\/td>\n27.34.2 Initializing VPI system task\/function callbacks <\/td>\n<\/tr>\n
494<\/td>\n27.34.3 Registering multiple system tasks and functions <\/td>\n<\/tr>\n
495<\/td>\n27.35 vpi_remove_cb()
27.36 vpi_scan() <\/td>\n<\/tr>\n
496<\/td>\n27.37 vpi_vprintf() <\/td>\n<\/tr>\n
497<\/td>\n28. Protected envelopes
28.1 General
28.2 Processing protected envelopes <\/td>\n<\/tr>\n
498<\/td>\n28.2.1 Encryption <\/td>\n<\/tr>\n
499<\/td>\n28.2.2 Decryption
28.3 Protect pragma directives <\/td>\n<\/tr>\n
501<\/td>\n28.4 Protect pragma keywords
28.4.1 begin
28.4.2 end
28.4.3 begin_protected <\/td>\n<\/tr>\n
502<\/td>\n28.4.4 end_protected
28.4.5 author <\/td>\n<\/tr>\n
503<\/td>\n28.4.6 author_info
28.4.7 encrypt_agent
28.4.8 encrypt_agent_info <\/td>\n<\/tr>\n
504<\/td>\n28.4.9 encoding <\/td>\n<\/tr>\n
505<\/td>\n28.4.10 data_keyowner
28.4.11 data_method <\/td>\n<\/tr>\n
506<\/td>\n28.4.12 data_keyname <\/td>\n<\/tr>\n
507<\/td>\n28.4.13 data_public_key
28.4.14 data_decrypt_key <\/td>\n<\/tr>\n
508<\/td>\n28.4.15 data_block
28.4.16 digest_keyowner
28.4.17 digest_key_method <\/td>\n<\/tr>\n
509<\/td>\n28.4.18 digest_keyname
28.4.19 digest_public_key <\/td>\n<\/tr>\n
510<\/td>\n28.4.20 digest_decrypt_key
28.4.21 digest_method <\/td>\n<\/tr>\n
511<\/td>\n28.4.22 digest_block <\/td>\n<\/tr>\n
512<\/td>\n28.4.23 key_keyowner
28.4.24 key_method
28.4.25 key_keyname <\/td>\n<\/tr>\n
513<\/td>\n28.4.26 key_public_key
28.4.27 key_block <\/td>\n<\/tr>\n
514<\/td>\n28.4.28 decrypt_license
28.4.29 runtime_license <\/td>\n<\/tr>\n
515<\/td>\n28.4.30 comment
28.4.31 reset <\/td>\n<\/tr>\n
516<\/td>\n28.4.32 viewport <\/td>\n<\/tr>\n
517<\/td>\nAnnex A (normative) Formal syntax definition
A.1 Source text
A.1.1 Library source text
A.1.2 Verilog source text
A.1.3 Module parameters and ports <\/td>\n<\/tr>\n
518<\/td>\nA.1.4 Module items <\/td>\n<\/tr>\n
519<\/td>\nA.1.5 Configuration source text
A.2 Declarations
A.2.1 Declaration types <\/td>\n<\/tr>\n
520<\/td>\nA.2.2 Declaration data types <\/td>\n<\/tr>\n
521<\/td>\nA.2.3 Declaration lists
A.2.4 Declaration assignments <\/td>\n<\/tr>\n
522<\/td>\nA.2.5 Declaration ranges
A.2.6 Function declarations
A.2.7 Task declarations <\/td>\n<\/tr>\n
523<\/td>\nA.2.8 Block item declarations
A.3 Primitive instances
A.3.1 Primitive instantiation and instances <\/td>\n<\/tr>\n
524<\/td>\nA.3.2 Primitive strengths
A.3.3 Primitive terminals
A.3.4 Primitive gate and switch types <\/td>\n<\/tr>\n
525<\/td>\nA.4 Module instantiation and generate construct
A.4.1 Module instantiation
A.4.2 Generate construct <\/td>\n<\/tr>\n
526<\/td>\nA.5 UDP declaration and instantiation
A.5.1 UDP declaration
A.5.2 UDP ports
A.5.3 UDP body <\/td>\n<\/tr>\n
527<\/td>\nA.5.4 UDP instantiation
A.6 Behavioral statements
A.6.1 Continuous assignment statements
A.6.2 Procedural blocks and assignments
A.6.3 Parallel and sequential blocks <\/td>\n<\/tr>\n
528<\/td>\nA.6.4 Statements
A.6.5 Timing control statements <\/td>\n<\/tr>\n
529<\/td>\nA.6.6 Conditional statements
A.6.7 Case statements
A.6.8 Looping statements
A.6.9 Task enable statements <\/td>\n<\/tr>\n
530<\/td>\nA.7 Specify section
A.7.1 Specify block declaration
A.7.2 Specify path declarations
A.7.3 Specify block terminals
A.7.4 Specify path delays <\/td>\n<\/tr>\n
532<\/td>\nA.7.5 System timing checks <\/td>\n<\/tr>\n
534<\/td>\nA.8 Expressions
A.8.1 Concatenations
A.8.2 Function calls
A.8.3 Expressions <\/td>\n<\/tr>\n
535<\/td>\nA.8.4 Primaries <\/td>\n<\/tr>\n
536<\/td>\nA.8.5 Expression left-side values
A.8.6 Operators
A.8.7 Numbers <\/td>\n<\/tr>\n
537<\/td>\nA.8.8 Strings
A.9 General
A.9.1 Attributes <\/td>\n<\/tr>\n
538<\/td>\nA.9.2 Comments
A.9.3 Identifiers <\/td>\n<\/tr>\n
539<\/td>\nA.9.4 White space <\/td>\n<\/tr>\n
540<\/td>\nAnnex B (normative) List of keywords <\/td>\n<\/tr>\n
541<\/td>\nAnnex C (informative) System tasks and functions
C.1 $countdrivers <\/td>\n<\/tr>\n
542<\/td>\nC.2 $getpattern <\/td>\n<\/tr>\n
543<\/td>\nC.3 $input
C.4 $key and $nokey
C.5 $list <\/td>\n<\/tr>\n
544<\/td>\nC.6 $log and $nolog
C.7 $reset, $reset_count, and $reset_value <\/td>\n<\/tr>\n
545<\/td>\nC.8 $save, $restart, and $incsave <\/td>\n<\/tr>\n
546<\/td>\nC.9 $scale
C.10 $scope
C.11 $showscopes
C.12 $showvars <\/td>\n<\/tr>\n
547<\/td>\nC.13 $sreadmemb and $sreadmemh <\/td>\n<\/tr>\n
548<\/td>\nAnnex D (informative) Compiler directives
D.1 `default_decay_time
D.2 `default_trireg_strength <\/td>\n<\/tr>\n
549<\/td>\nD.3 `delay_mode_distributed
D.4 `delay_mode_path
D.5 `delay_mode_unit
D.6 `delay_mode_zero <\/td>\n<\/tr>\n
550<\/td>\nAnnex E (normative) acc_user.h (deprecated) <\/td>\n<\/tr>\n
551<\/td>\nAnnex F (normative) veriuser.h (deprecated) <\/td>\n<\/tr>\n
552<\/td>\nAnnex G (normative) vpi_user.h <\/td>\n<\/tr>\n
567<\/td>\nAnnex H (informative) Encryption\/decryption flow
H.1 Tool vendor secret key encryption system
H.1.1 Encryption input <\/td>\n<\/tr>\n
568<\/td>\nH.1.2 Encryption output
H.2 IP author secret key encryption system
H.2.1 Encryption input <\/td>\n<\/tr>\n
569<\/td>\nH.2.2 Encryption output
H.3 Digital envelopes <\/td>\n<\/tr>\n
570<\/td>\nH.3.1 Encryption input <\/td>\n<\/tr>\n
571<\/td>\nH.3.2 Encryption output <\/td>\n<\/tr>\n
572<\/td>\nAnnex I (informative) Bibliography <\/td>\n<\/tr>\n
573<\/td>\nIndex <\/td>\n<\/tr>\n<\/table>\n","protected":false},"excerpt":{"rendered":"

IEEE Standard for Verilog Hardware Description Language<\/b><\/p>\n\n\n\n\n
Published By<\/td>\nPublication Date<\/td>\nNumber of Pages<\/td>\n<\/tr>\n
IEEE<\/b><\/a><\/td>\n2005<\/td>\n<\/td>\n<\/tr>\n<\/tbody>\n<\/table>\n","protected":false},"featured_media":399532,"template":"","meta":{"rank_math_lock_modified_date":false,"ep_exclude_from_search":false},"product_cat":[2644],"product_tag":[],"class_list":{"0":"post-399530","1":"product","2":"type-product","3":"status-publish","4":"has-post-thumbnail","6":"product_cat-ieee","8":"first","9":"instock","10":"sold-individually","11":"shipping-taxable","12":"purchasable","13":"product-type-simple"},"_links":{"self":[{"href":"https:\/\/pdfstandards.shop\/wp-json\/wp\/v2\/product\/399530","targetHints":{"allow":["GET"]}}],"collection":[{"href":"https:\/\/pdfstandards.shop\/wp-json\/wp\/v2\/product"}],"about":[{"href":"https:\/\/pdfstandards.shop\/wp-json\/wp\/v2\/types\/product"}],"wp:featuredmedia":[{"embeddable":true,"href":"https:\/\/pdfstandards.shop\/wp-json\/wp\/v2\/media\/399532"}],"wp:attachment":[{"href":"https:\/\/pdfstandards.shop\/wp-json\/wp\/v2\/media?parent=399530"}],"wp:term":[{"taxonomy":"product_cat","embeddable":true,"href":"https:\/\/pdfstandards.shop\/wp-json\/wp\/v2\/product_cat?post=399530"},{"taxonomy":"product_tag","embeddable":true,"href":"https:\/\/pdfstandards.shop\/wp-json\/wp\/v2\/product_tag?post=399530"}],"curies":[{"name":"wp","href":"https:\/\/api.w.org\/{rel}","templated":true}]}}