{"id":248056,"date":"2024-10-19T16:20:11","date_gmt":"2024-10-19T16:20:11","guid":{"rendered":"https:\/\/pdfstandards.shop\/product\/uncategorized\/bs-en-62343-4-12016\/"},"modified":"2024-10-25T11:28:47","modified_gmt":"2024-10-25T11:28:47","slug":"bs-en-62343-4-12016","status":"publish","type":"product","link":"https:\/\/pdfstandards.shop\/product\/publishers\/bsi\/bs-en-62343-4-12016\/","title":{"rendered":"BS EN 62343-4-1:2016"},"content":{"rendered":"
IEC 62343-4-1:2016 describes and provides specifications for a software and hardware interface for the 1 x 9 wavelength selective switch. These switches can be controlled by resident firmware with this interface. This standard addresses the configuration and function to control a WSS. This interface is intended to enable a user or host to retrieve the switch status and\/or adjust relevant switch and attenuation settings.<\/p>\n
PDF Pages<\/th>\n | PDF Title<\/th>\n<\/tr>\n | ||||||
---|---|---|---|---|---|---|---|
6<\/td>\n | CONTENTS <\/td>\n<\/tr>\n | ||||||
7<\/td>\n | FOREWORD <\/td>\n<\/tr>\n | ||||||
9<\/td>\n | INTRODUCTION <\/td>\n<\/tr>\n | ||||||
10<\/td>\n | 1 Scope 2 Normative references 3 Terms, definitions and abbreviations 3.1 Terms and definitions 3.2 Abbreviations <\/td>\n<\/tr>\n | ||||||
11<\/td>\n | 4 Basic configuration of WSS interface Figures Figure 1 \u2013 Basic configuration of WSS interface <\/td>\n<\/tr>\n | ||||||
12<\/td>\n | 5 Software interface <\/td>\n<\/tr>\n | ||||||
13<\/td>\n | Tables Table 1 \u2013 Software interface <\/td>\n<\/tr>\n | ||||||
14<\/td>\n | Table 2 \u2013 DPRAM memory map <\/td>\n<\/tr>\n | ||||||
15<\/td>\n | 6 Hardware interface \u2013 Electrical connector <\/td>\n<\/tr>\n | ||||||
16<\/td>\n | Annex A (informative) Hardware interface details Table A.1 \u2013 Connector form Table A.2 \u2013 Pin assignment <\/td>\n<\/tr>\n | ||||||
17<\/td>\n | Table A.3 \u2013 Supply voltages and currents Table A.4 \u2013 Low voltage TTL thresholds Table A.5 \u2013 Power consumption <\/td>\n<\/tr>\n | ||||||
18<\/td>\n | Annex B (informative) DPRAM memory map details and timing charts Table B.1 \u2013 DPRAM memory map specification A <\/td>\n<\/tr>\n | ||||||
19<\/td>\n | Table B.2 \u2013 DPRAM memory map specification B <\/td>\n<\/tr>\n | ||||||
28<\/td>\n | Table B.3 \u2013 Signal time specification <\/td>\n<\/tr>\n | ||||||
29<\/td>\n | Figure B.1 \u2013 DPRAM READ CYCLE timing <\/td>\n<\/tr>\n | ||||||
30<\/td>\n | Figure B.2 \u2013 DPRAM WRITE CYCLE timing Figure B.3 \u2013 POWER ON timing <\/td>\n<\/tr>\n | ||||||
31<\/td>\n | Figure B.4 \u2013 START timing Figure B.5 \u2013 MASTER RESET timing <\/td>\n<\/tr>\n | ||||||
32<\/td>\n | Figure B.6 \u2013 SOFT RESET timing Figure B.7 \u2013 DPRAM BUSY timing <\/td>\n<\/tr>\n | ||||||
33<\/td>\n | Figure B.8 \u2013 ALARM timing <\/td>\n<\/tr>\n | ||||||
34<\/td>\n | Bibliography <\/td>\n<\/tr>\n<\/table>\n","protected":false},"excerpt":{"rendered":" Dynamic modules – Software and hardware interface. 1 x 9 wavelength selective switch<\/b><\/p>\n |