BS IEC 62050:2005
$215.11
VHDL register transfer level (RTL) synthesis
Published By | Publication Date | Number of Pages |
BSI | 2005 | 128 |
Specifies a standard for use of very high-speed integrated circuit hardware description language (VHDL) to model synthesizable register-transfer level digital logic. A standard syntax and semantics for VHDL register-transfer level synthesis is defined. The subset of the VHDL language, which is synthesizable, is described, and nonsynthesizable VHDL constructs are identified that should be ignored or flagged as errors.