IEEE 1149.6 2016

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IEEE Approved Draft Standard for Boundary-Scan Testing of Advanced Digital Networks

Published By	Publication Date	Number of Pages
IEEE	2016	230

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Description

Revision Standard – Active. This standard augments IEEE Std 1149.1 to improve the ability for testing differential and/or ac-coupled interconnections between integrated circuits on circuit boards and systems.

PDF Catalog

PDF Pages	PDF Title
1	IEEE Std 1149.6™-2015 Front Cover
3	Title page
5	Important Notices and Disclaimers Concerning IEEE Standards Documents
8	Participants
9	Introduction
12	Contents
15	Important Notice 1. Overview 1.1 Scope 1.2 Purpose
16	1.3 Organization of the standard
17	1.4 Context 1.5 Objectives
18	2. Normative references 3. Definitions and acronyms 3.1 Definitions
24	3.2 Acronyms
25	4. Technology
26	4.1 Signal pin types 4.2 Signal coupling and coupling combinations
32	4.3 The effects of defects
34	4.4 Defects targeted by the standard
35	4.5 Differential termination and testability
38	4.6 Test signal implementation
42	4.7 Test receiver support for ac testing instructions
46	4.8 Test receiver support for the (DC) EXTEST instruction
48	4.9 A general test receiver for dc and ac testing instructions
50	4.10 Boundary-scan capture data versus configuration
52	4.11 Noise sources and sensitivities
56	5. Instructions 5.1 IEEE Std 1149.1 instructions 5.2 AC testing instructions
59	5.3 The EXTEST_PULSE instruction
61	5.4 The EXTEST_TRAIN instruction
64	5.5 ac test signal generation 6. Pin implementation specifications 6.1 Pin identification
65	6.2 Input test receivers
97	6.3 Output drivers
100	6.4 Bidirectional pins
104	6.5 AC/DC selection cells
106	7. Conformance and documentation requirements 7.1 Conformance
107	7.2 Documentation
109	7.3 BSDL package for Advanced I/O description (STD_1149_6_2015)
112	7.4 BSDL extension structure
115	7.5 BSDL attribute definitions
137	7.6 Example BSDL
156	7.7 PDL procedures for programmable ac pins
161	7.8 Example PDL procedures for programmable ac pins
187	Annex A (informative) Applications and tools A.1 Chip compliance checking and BSDL and PDL verification
193	A.2 Functional verification A.3 Board interconnection testing
203	Annex B (informative) Noise rejection in edge-detecting mode B.1 Noise rejection by bandwidth limitation
205	B.2 Noise rejection by slew rate limitation
206	Annex C (informative) Advanced I/O boundary-scan register cells C.1 AC/DC selection cell AC_SelX C.2 AC/DC selection cell AC_SelU
207	C.3 Output data cell AC_1 (supports INTEST)
208	C.4 Output data cell AC_2 C.5 Bidirectional output cell AC_7 (supports INTEST)
209	C.6 Bidirectional output cell AC_8
210	C.7 Self-monitoring output cell AC_9 (supports INTEST)
211	C.8 Self-monitoring output cell AC_10 C.9 AC_40 and AC_41 cells
212	C.10 AC cell mode controls
213	Annex D (informative) Test receiver design examples D.1 LVDS with normal board coupling
219	D.2 LVDS with alternative board coupling
220	D.3 LVDS with on-chip coupling
222	D.4 LVPECL (low-voltage pseudo emitter-coupled logic)
224	D.5 LVPECL with guaranteed on-board ac coupling
225	D.6 LVPECL with on-chip coupling
227	Annex E (informative) A proposed “INITIALIZE” instruction
228	Annex F (informative) Bibliography
230	Back Cover